1. Field of the Invention
The present invention relates to a level converter and a semiconductor device, and particularly to a level converter and a semiconductor device for suppressing an attenuation of a signal communicated across wide band.
2. Description of Related Art
In recent years, an operating speed of a semiconductor device is increasing. Thus a frequency of a signal transmitted and received between semiconductor devices is increasing. To transmit/receive such a high frequency signal, generally an amplitude of the signal is reduced and the signal is treated as a differential signal. By reducing the amplitude of the signal, it is possible to generate a signal that changes at high speed without increasing the current driving capability of output buffer. Furthermore, by treating the signal as a differential signal, it is possible to improve noise immunity of a small amplitude signal. For such a small amplitude signal, there is a CML (Current Mode Logic) level signal having a smaller amplitude than the voltages such as a power supply voltage and ground voltage. On the other hand, a signal having a large amplitude from the ground voltage to power supply voltage is referred to as a CMOS (Complementary Metal Oxide Semiconductor) level signal.
An example of a circuit processing a CML level signal is shown in FIGS. 12 and 13. FIG. 12 shows a transmitting circuit 100. The transmitting circuit 100 is a circuit for transmitting a CML level signal and converts a CMOS level signal input in parallel to a CML level signal output in serial. Here, the CML level signal performs a differential operation and a central voltage of the amplitude is close to the ground voltage. This signal is referred to as a PMOS-CML level signal. On the other hand, a signal that performs a differential operation and a central voltage of the amplitude is close to the power supply voltage is referred to as a NMOS-CML level signal.
The transmitting circuit 100 includes a parallel to serial converter 101, CMOS amplifier 102 and PMOS-CML amplifier 103. The CMOS amplifier 102 is composed of CMOS transistors. Furthermore, the CMOS amplifier 102 generates a differential signal having a CMOS level from a single-end signal having a CMOS level and then outputs the signal. The parallel to serial converter 101 converts a parallel signal input from the CMOS amplifier 102 into a serial signal and then outputs the signal. At this time, the parallel to serial converter 101 converts a CMOS level signal into a PMOS-CML level signal. Therefore, in order to generate a PMOS-CML level signal, the parallel to serial converter 101 has the PMOS-CML amplifier that includes a differential pair composed of PMOS transistors. The PMOS-CML amplifier 103 is an amplifier having a differential pair composed of PMOS transistors. Moreover, the PMOS-CML amplifier 103 matches an output impedance with load resistances RLt and RLb that are connected to an output of the PMOS-CML amplifier and outputs a PMOS-CML level signal. The PMOS-CML level signal to be output is generated based on an output from the parallel to serial converter 101.
On the other hand, the receiving circuit 200 of FIG. 13 receives a CML level signal and converts the CML level signal input in serial to a CMOS level signal output in parallel. Here, this CML level signal is a PMOS-CML level signal.
The receiving circuit 200 includes a serial to parallel converter 201, PMOS-CML amplifier 202, CMOS amplifier 203 and level converters 204. The PMOS-CML amplifier 202 has a differential pair composed of PMOS transistors. The PMOS-CML amplifier 202 operates as an input buffer for receiving a PMOS-CML level signal. The serial to parallel converter 201 converts a serial signal input from the PMOS-CML amplifier 202 into a parallel signal and then outputs the signal. The serial to parallel converter 201 includes a PMOS-CML amplifier having a differential pair composed of PMOS transistors so as to handle PMOS-CML level signals. The level converters 204 are differential amplifiers as shown in FIGS. 14 and 15, for example, that convert a signal input at a CML level into a signal of a CMOS level. Another example of the level converter 204 is disclosed in Japanese Unexamined Patent Application Publication No. 6-152379, 9-261032 and 2004-128747. The CMOS amplifier 203 is composed of CMOS transistors.
To process a CML level signal having a level close to the ground potential, an amplifier having a differential pair composed of NMOS transistors cannot be used. This is because that for such a low level signal, a gate voltage of the NMOS transistors does not exceed the threshold voltage. Therefore, to process such a low signal level differential signal, the differential pair must be composed of PMOS transistors.
However, it is generally known that as PMOS transistors have carrier mobility lower than NMOS transistors, a frequency of signal that can be communicated is poorer than NMOS transistors. Therefore, we have now discovered that to process a CML level signal having a low signal level, there is a problem that a signal with high frequency cannot be communicated by a circuit using the abovementioned PMOS-CML amplifier.